1. Field of the Invention
The present invention relates to an information processing unit. In particular, it relates to an information processing unit, which performs clock switching dynamically.
2. Description of the Prior Art
Typically, reduction of power consumption has been a common problem for information processing units including a central processing unit (CPU). In particular, there is an urgent need to reduce power consumption since batteries are used as power supply for portable information processing units, such as those in mobile phones or mobile terminals. Therefore, in order to reduce power consumption, for example, the clock for an inactive circuit section is halted, or the clock for a circuit section in which high-speed operation is not required is switched to low speed.
In order to achieve such processing, a system typically includes a power management unit. This power management unit performs detection or prediction of an inactive circuit section, and issues an instruction to halt the clock signal related to that inactive circuit section in accordance with that detection or prediction. It is also necessary to issue an instruction to switch to low speed the clock that drives a circuit section that is in operation mode and where processing time is unimportant.
If data transfer (hereafter also referred to as “direct memory access” or “DMA”) between memory and peripheral equipment is performed on the bus without using the CPU when performing a clock switch or clock halt, the data transfer may fail. For example, when a memory read cycle of DMA is being executed by burst transfer in which data is consecutively output while incrementing a memory address for each clock cycle, if a clock edge cannot be received within a prescribed period because of a clock being halted or de-accelerated, the bus master may lose the data that immediately follows the clock switch. Accordingly, it is necessary to perform a clock switch or clock halt at a time where DMA is not being performed on the bus.
A means for solving such problems is disclosed in Japanese Patent Application Laid-open No. Hei 7-152499. In this document, an information processing unit in which a clock control circuit monitors a bus request signal from a peripheral processor, or a master monitors a signal for requesting use of a bus is proposed.
FIG. 2 illustrates a configuration of an information processing unit according to this Japanese Patent Application Laid-open No. Hei 7-152499. In Japanese Patent Application Laid-open No. Hei 7-152499, as shown in FIG. 2, presence of a bus request signal from a master 1 (10) and master 2 (11), which are peripheral processors, is conveyed to a power management unit 4 as a clock request. The power management unit 4 then applies control so as to halt or de-accelerate the clock in order to achieve power saving when there is no bus request signal.
Nevertheless, with the information processing unit disclosed in Japanese Patent Application Laid-open No. Hei 7-152499, a clock switch cannot be performed when a bus request signal is consecutively asserted by a plurality of master devices. Accordingly, the clock cannot be switched to low speed and it must continue to operate with a high-speed clock and consume excess power. In the opposite case, when high-speed operation is requested while operating with a low-speed clock, the clock naturally cannot be switched to a high-speed clock if the bus request signal is being consecutively asserted.
In addition, other problems exist where even in the case where the bus request signal is de-asserted (disabled), there is a case where once becoming a bus master, data transfer is continued by de-asserting the bus request signal, such as during burst transfer. Therefore, it is not possible to determine whether or not data transfer is performed from only the presence of a bus request signal. Moreover, a device that becomes the bus master must continue to assert (enable) the bus request signal until the data transfer ends. Therefore, an arbiter cannot determine whether this bus request signal is for the current transfer or for a new transfer, making high-speed arbitration impossible. In other words, with the information processing unit disclosed in the Japanese Patent Application Laid-open No. Hei 7-152499, the compatibility of the information processing unit becomes limited.